System Information

risg.tuwien.ac.at

Silicon Graphics' Onyx platform combines the multiprocessing power of a supercomputer with the world's most advanced graphics architecture. Onyx was designed with a flexible and scalable open systems approach that provides users with superior performance and a wealth of development tools and libraries.

Performance : RISG
Multiprocessing : RISG
I/O Architecture : RISG
FDDI & Ethernet - Interface
Disks on RISG
Onyx Graphics : RISG
Technical Specifications : RISG

expandable Devices:

Virtual Reality - Device

RISG - Deskside Chassis

Features:

Multiprocessing Support: two MIPS R4400 CPUs for balanced integer & floating point performance
High-Capacity Memory: memory 256 MB 2-way interleaving
Powerful I/0 System: one POWERchannel-2 I/O board delivers up to 320MB/sec I/O bandwidth
High-Bandwidth VME Bus: three VME slots with 5OMB/sec bus
RealityEngine2 Graphics
SCSI-2 FAST/WIDE Disk Technology

Multiprocessing

The multiprocessing power of Onyx graphics supercomputers begins at the core, with the MlPS (r) R4400 (tm) 64-bit RISC microprocessor. The combination of two R4400s working together gives RISG users the kind of computing performance typically associated with today's most advanced supercomputers.

MIPS R4400 Processor

64-bit 150Mhz MIPS R4400 CPU: 32KB on-chip primary cache
1MB Secondary Cache: available for maximum application throughput

I/O Architecture

Advanced Throughput and I/O Power
RISG has a advanced and well balanced I/O subsystem. POWERchannel-2 (tm) is the fundamental component of the I/O subsystem and supports sustained data transfer rates up to 320 MB per second per board.

The POWERchannel-2 board contains:

a l0 MB/sec Ethernet controller,
two 20 MB/sec FAST/WIDE 16-bit SCSI-II controllers (configurable as single-ended or differential),
a 50 MB/sec VME controller,
two 19.2 KB RS232 serial ports,
a 38.4 KB RS422 serial port,
a parallel port, and
a high-speed 150MB/sec graphics connection.

Additional expansion and customization is available with optional daughter boards (HIO modules) that plug directly onto the POWERchannel-2. Added disk throughput and capacity is achieved with SCSI-II HIO modules. Each module adds three additional 20 MB/sec SCSI-II controllers and up to two SCSI-II HIO modules may be added per POWERchannel-2 board. For high speed networking performance, optional HiPPI and FDDI HIO modules can be added.

The optimized l/O architecture arms Onyx for a wide range of throughput intensive applications such as satellite image acquisition and analysis, earth sciences, remote sensing, and video on demand.

POWERchannel-2 I/O subsystem

One to four POWERchannel-2 boards in an Onyx rack
320 MB/sec I/O bandwidth per POWERchannel-2
VME64 controller with 50 MB/sec bus
High-speed graphics connection
Two FAST/WIDE 16-bit SCSI-2 controllers
Optional expansion to add up to six additional SCS1-2 controllers, HiPPI, and FDDI connections

RealityEngine2 Graphics Subsystems

Features:

Geometry Engine: the heart of the RealityEngine2 graphics subsystem
12 Geometry Engines Per RealityEngine2 Pipeline- delivers 1.2 GFLOPS of processing power, RealityEngine2 can render 1.6M triangles per second.
Raster Manager(RM) Board: provides the pixel-fill capabilities for the system - Onyx RealityEngine2 supports up to four RM boards per graphics pipeline
40MB Frame Buffer per RM: 4 RM boards allows for multisample anti-aliasing on screen resolutions up to 1600 x 1200. 4 RMs provides an overall frame buffer size of up to 2560 x 2048 and 1024 bits per pixel.
4MB or 16MB of Texture Memory available for all Onyx systems
Fast Fill Rate: 80 million pixels per second, expandable to 320 million pixels per second through the use of four RM boards
Display Generator Board: takes the rendered frames and outputs them as analog video, or as a digital stream to the Sirius Video or MultiChannel Option boards
Programmable Pixel Clock: allows the Onyx to drive a wide variety of resolutions, from 640x480tol920x 1035 and 1600 x 1200
Built-In Encoder: provides NTSC, PAL and S-video outputs for direct-to-VCR recording of an area of the high resolution screen

RealityEngine2: Interactive Realism for Reality and Beyond

RealityEngine2 combines advanced parallel processing technology with custom chip-level integration and up to 160MB of frame-buffer memory. The result is a multipurpose graphics supercomputing platform that outperforms dedicated, single-purpose proprietary hardware solutions at a fraction of the cost. The open systems performance that RealityEngine2 provides is ideal for applications such as image processing, industrial design, molecular modeling and visual simulation. The RealityEngine2 architecture offers the industry's fastest polygon, pixel and vector performance over two million shaded points, lines and polygons per second, with pixel fill rates that can be scaled to 320 million textured, anti-aliased pixels per second. Onyx can be made even more powerful by adding broadcast- quality video input and output options, extra texture memory and multiple displays. Users can configure up to three RealityEngine2 subsystems in a single Onyx chassis.

Technical Specifications of the RISG Onyx

Processor Data

MIPS R4400 MC 64-bit RISC CPU

---------------------------------------------------------
Quantity         2                                   
Clock Frequency  150 MHz                                   
Primary Cache    16KB on-chip instruction cache 16KB on-    
                 chip data cache                           
Secondary Cache  1 MB per of combined secondary cache per   
                 processor                                 
                                                           
---------------------------------------------------------

Graphics

RealityEngine2

1.6M t-mesh triangles/sec 930K textured t-mesh triangles/sec 80/160/320M textured, anti-aliased pixels/sec Hardware texture mapping
Real-time anti-aliasing
VGA up to 1600 x 1200 and HDTV display
Advanced stereo modes
Hardware image processing acceleration
48-bit RGBA color, quad-buffered (192-bits total)
1024-bits per pixel
40 to 160MB frame buffer
NTSC/PAL/S-Video output

Systems Bus

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Bandwidth  1.2GB/sec, parity protected     
   
Size       256-bit wide data path,            
           40-bit wide physical Address path  
                                              
--------------------------------------------

Memory subsystem


---------------------------------------------
Physical Memory       256 Mb, ECC protected 
 
Interleaving          1,2,4, or 8-way          
                                               
---------------------------------------------

High-Speed l/O Subsystem

------------------------------------
Bus Type      SGI HIO bus             
Bandwidth     320MB/sec per HIO bus   
No. of Buses  1 to 4                  
No. of Slots  1 to 8                  
                                      
------------------------------------

Industry Standard I/O Subsystem

-------------------------------------
Bus Type       VME64 bus               
Bandwidth      50MB/sec per VME64 bus   
No. of Buses   1 to S                   
No. of Slots   3 to 24                  
                                       
-------------------------------------

Mass Storage

-----------------------------------------------------------
Interfaces        Up to 32 SCSI-2 channels 
                  
Protocols         SCSI-2, FAST/WIDE, 
                  single-ended or differential
                                      
Max. Bandwidth    20MB/sec per channel
                        
Device Capacity   2GB, formatted                             
                                                             
-----------------------------------------------------------

Removable Media

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SCSI Devices     CDROM, DAT, 8mm tape drive, 1/4" cartridge tape  
                                                                  
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Communications

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Integrated Serial I/O      Up to 16 serial ports Ethernet, SCSI-2  
Integrated Parallel I/O    Up to 4 parallel ports                  
VME Controllers            Ethernet, FDDI                          
SGI HIO Controllers        FDDI, HiPPI, SCSI-2                     
                                                                   
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compiled by Elmar Schmidinger
eschmidi@RISG.archlab.tuwien.ac.at

Edited by Borislav Petrov
bobo@email.archlab.tuwien.ac.at